The present invention relates to a decoupling capacitor and a semiconductor integrated circuit device including a decoupling capacitor.
In recent years, progress has been made to increase the operation speed and enlarge the scale of semiconductor integrated circuit devices (semiconductor devices). This has increased power consumption, which is a factor that leads to the generation of power supply noise. Power supply noise destabilizes the operation of the semiconductor device. The power supply noise may be reduced by arranging a decoupling capacitor (inter-power supply capacitor cell) between a high potential power supply wiring and a low potential power supply wiring of the semiconductor device. It is required to reduce manufacturing variations in semiconductor devices caused by decoupling capacitors.
In the prior art, a semiconductor integrated circuit device, which includes a logic cell, is provided with a decoupling capacitor (inter-power supply capacitor cell) for suppressing fluctuations in power supply voltage and preventing erroneous functioning of the logic cell. The inter-power supply capacitor cell is configured by a P-channel MOS transistor and an N-channel MOS transistor connected between a high potential power supply and a low potential power supply.
The source and the drain of the P-channel MOS transistor are connected to the high potential power supply. The gate of the P-channel MOS transistor is connected to the low potential power supply. Then, a gate oxidized film is formed to form a capacitor element. The source and the drain of the N-channel MOS transistor are connected to the low potential power supply. A diffusion layer and a gate wire on which a gate oxidized film is applied forms a capacitor element. The capacitor element has a capacitance determined by the area in which the diffusion layer and the gate wire overlap each other.
The gate oxidized film has become thinner due to the miniaturization of transistors over recent years. This has resulted in the possibility of the occurrence of electrostatic discharge (ESD) damage in the prior art capacitor element, the gate of which is connected to the power supply wiring. Japanese Laid-Open Patent Publication No. 2003-86699 proposes a decoupling capacitor in which a P-channel MOS transistor and an N-channel MOS transistor each have a gate and a drain connected to each other to prevent ESD. Such P-channel MOS transistor and N-channel MOS transistor form a capacitor element and a resistor connected in series between the high potential power supply and the low potential power supply. Therefore, the decoupling capacity includes a gate capacitor and a resistor, which is for countering ESD.